1. Field of the Invention
The invention relates to interface circuits for binary signal processing devices. More particularly, the invention relates to a slew rate control aspect of such interface circuits.
2. Description of the Prior Art
Numerous circuit applications require an interface circuit, such as an input circuit or an output circuit, for transferring a logic value between two terminals. In the simplest form, a drive transistor has a control electrode coupled to a first terminal and main current path which couples the second terminal to a selected power supply. When a signal received at the first terminal turns the drive transistor on, the other terminal is pulled to the potential of the power supply. In this way, the second terminal can be supplied with a different current than the driving signal at the first terminal.
One common use for interface circuits is for binary signal processing devices, such as standard and programmable logic devices. These devices have a core with a great number of logic arrays each of which output a logic signal that must be coupled to associated input/output pins of the device. The purpose of interface circuits is to ensure that data is communicated correctly with other devices, such as over a communication bus, and these circuits are accordingly designed to withstand dangers which they may reasonably be expected to encounter.
A commonly used interface circuit is a tri-state output buffer, which is characterized by its three possible output states: "low", "high" and "tri-state". The typical tri-state buffer has an output terminal, a pull-up device to selectively couple the output to a first supply and a pull-down device to selectively couple the output to a second, lower supply. The buffer is in the "tri-state" mode when both of the pull-up and pull-down devices are in the non-conductive "OFF" state, thereby presenting a high impedance to the output.
U.S. Pat. No. 5,500,611 (Popat et al) shows a tri-state output buffer with a high and a low power mode. The low power mode is provided by a weak pull up device and is used in a sleep mode, while the high power mode is provided by a strong pull up device. Both pull-up devices include normally cut-off FET's with a main current channel coupled to an output node and to a supply terminal. The strong pull-up device differs from the weak pull up device in that when the FETs are enabled the main current path of the weak pull-up device has a higher resistance than the main current path of the strong pull up device. Thus, when the weak pull up device is activated, its higher resistance provides a smaller current to the output pin than when the strong device is activated, in a ratio of 1:4. The different resistances are obtained through selection of different lengths and widths of the main current paths of the FETS.
In binary signal processing devices having a large number of output pins and associated interface circuits, power surges are possible when a large number of drive transistors are nearly simultaneously enabled, due to switching transients. However, minimizing power consumption whether in the steady state as in Popat or during switching often conflicts with minimum current requirements for external devices connected to the interface circuit. For example, standards for communication buses often have minimum current levels to be maintained. A PCI bus must maintain an AC drive current of -40 mA pull-up and 53 mA pull-down.